Data scrambler

This page compares Synchronous scrambler vs Self synchronizing scrambler and mentions difference between synchronous scramblerand self synchronizing scrambler used in data communication including their advantages (benefits) and disadvantages (drawbacks).Introduction:In wireless communication, scrambler is used to remove long sequence of ones and zeros by randomization of data.It is used before FEC encoder or modulator or line encoder. Scrambler is used at the transmitter side.Descambler is used at the receiver side to recover original bit patternfrom randomized data bits. The same is shown in the physical layer of wimax as per IEEE 802.16 standard.There are two main functions of scrambler in the system. • It provides more transitions in the data by removing long string of similar data bits i.e. 1s and 0s. This helps in accuate timing recoveryat the receiver. • It disperses energy on carrier signal and hence reduces ICI (Inter Carrier Interference). • The scrambling concept is used in R8ZS and HDB3 coding techniques to maintain DC balance. Synchronous scrambler | Additive scramblerIt uses LFSR (Linear Feedback Shift Register) togenerate PRBS (Pseudo Random Binary Sequence) sequence or pre-stored PRBS is used.Synchronous scrambler transforms data stream by using modulo-2 sum of input data andPRBS sequence as shown in the figure. Hence synchronous scrambler is also knownas additive scrambler. The circuit is as per PRBS generator 1 + X14 + X15 polynomial.Figure-1 : Synchronous scrambler and descrambler circuit The same SYNC word is used for scrambler and descrambler at the transmit and receive end to enablesynchronous operation of both.Advantages of Synchronous scramblerFollowing are the benefits or advantages of Synchronous scrambler. ➨It offers error detection capability. ➨It removes long string of zeros and ones and provide more transitions in the data pattern to makesynchronization easier without the need of separate clock signal. ➨It does not have any DC components. Disadvantages of Synchronous scramblerFollowing are the drawbacks or disadvantages of Synchronous scrambler. ➨It fails to generate random sequences in worst case conditions. ➨It should be reset by SYNC word otherwise massive error propagation occurs. Self synchronizing scrambler | Multiplicative scramblerThe scrambler and descrambler circuit for self synchronizing scrambler and descrambler is shown inthe figure. It does not require frame SYNC word for synchronization unlike synchronous scrambler.Hence it is called self-synchronizing scrambler.This scrambler performs multiplication of input by transfer function in Z-space.Hence self synchronizing is also known as Multiplicative scrambler.Figure-2 : Self synchronizing scrambler and descrambler circuit They are defined by polynomial 1 + X14 + X15.Multiplicative scrambler is recursive where as descrambler is non-recursive.Advantages of Self synchronizing scramblerFollowing are the benefits or advantages of Self synchronizing scrambler. ➨It does not require SYNC word called "SEED" for its operation unlike synchronous scrambler. ➨The other advantages are similar to the one listed in synchronous scrambler

Long as no line errors occur. FIG. 2 is a simplified block diagram of the improved scrambler according to this invention. To the basic scrambler 25, analogous to elements 11, 12, and 13 of FIG. 1, are added auxiliary delay unit 26 and monitoring logic 28. Basic scrambler 25 operates as previously described to complement the input data on line 20 in modulo-two adder 22 over control line 24. If the undesirable data input period is longer than the number of stages rovided in the basic scrambler, additional stages of storage or delay are furnished in auxiliary delay unit 26 at the output of basic scrambler 25. There is no direct feedback from auxiliary delay 26 to the data input sequence. However, output leads 27 from delay 26 are spaced from the input to scrambler 25 by the respective lengths of undesired sequences to be monitored. Monitoring logic 28 compares the outputs on leads 27 with the input to basic scrambler 25 and if they continuously match, complements the input data bit over lead 23 at modulo-two adder 21. The undesired sequence is thereby broken up and the output of the system on line 29 is forced to be of relatively long period. The improved descrambler is the same as the scrambler of FIG. 2 with data input 20 and output line 29 interchanged. The arrowheads at points 20, 29 and between adders 21 and 22 are necessarily reversed. Two basic types of self-synchronizing, digital data scramblers have been devised. They are the single-counter and multicounter types. The block diagram of FIG. 2 is regarded as generic to both types. The block diagram of FIG. 3 depicts the single-counter scrambler according to this invention. Here shift register stages SR-l to SRM, generally designated 11, adders 13 and 14 and multipliers 0 through c constitute together the basic scrambler as in FIG. 1. Auxiliary shift register stages SRSl to SR-S2, generally designated 26, constitute the auxiliary delay 26 of FIG. 2. Assume that there are periodic sequences of length S1 and S2, each greater than m, the number of stages in the basic scrambler. Then the output of stage SR-Sl is delayed by S1 bit intervals from the input to stage SR1. Similarly, the output of stage SR-S2 is delayed S2 bit intervals from the input to stage SR1. Monitoring logic comprises single-counter 35 with a threshold reached after t counts, modulo-two adder 32 for comparing the output of stage SRSl with the input to stage SR-l, modulo-two adder 33 for comparing the output of stage SR-S2 with the input to stage SRI, AND-gate 34 for combining the significant nonzero outputs of adders 32 and 33 to reset counter 35. Adders 32 and 33 have nonsignificant or zero outputs when their respective inputs are identical, i.e., when a periodic sequence of length S1 or S2 is present on the data input. In this case there will be no resetting output and counter 35 will advance toward its threshold. 0n the other

Data bit and the delayed data bits, spaced along the sequential filter by the lengths of several such deleterious sequence periods, are compared and control outputs are generated whenever there is a match. A single synchronously advanced counter is allowed to reach a predetermined threshold in the presence of a sustained matching control signal. Upon reaching threshold the prevailing data bit is complemented to prevent an undesired input sequence from appearing on the channel. The counter is reset when it reaches threshold as well as in the absence of a matching control signal. According to another aspect of the invention, the number of stages of delay in the sequential filter is also extended, as necessary, beyond the range of the basic scrambler and descrambler to the length of the longest periodic data sequence it is desired to break up. Comparison circuits, including zero-level slicers, are established between the input to the basic scrambler and taps on the extended scramber corresponding to the length of each undesired periodic sequence. An individual monitoring counter with preassigned threshold is then provided for each comparator circuit. The counter outputs are further buffered to complement the prevailing data bit whenever any of the counters reaches threshold. At the same time all counters are reset. The corresponding descrambler in either case is the complement of the transmitting scrambler with feedforward paths rather than feedback paths. Whereas the length of the basic scrambler is determined in the binary case by the shortest random channel sequence allowable, the length of the extended scrambler is determined by the length of the longest undesired sequence. However, it will be understood that where the basic scrambler is as long as, or longer than, the undesired sequence the monitoring tap may be included within the length of the basic scrambler. An advantage of this invention is that the level of tones produced by the unscrambled sequence is reduced by a factor equal to the ratio of the length of the unscrambled periodic sequence to that of the scrambled sequence. The scrambled sequence will also have as many low-level tones as the number of high-level tones in the unscrambled sequence multiplied by the reciprocal of this same factor. Another advantage of this invention is that the scrambled sequence will have half as many transitions for synchronization purposes as there are digits in the sequence. A feature of this invention is that scramblers and descramblers constructed according to the principles of this invention are capable of implementation by wellknown logic circuits. DESCRIPTION OF DRAWING Additional objects, features and advantages of this invention will be appreciated from a consideration of the following detailed description and the drawing in which: FIG. 1 is a block diagram of the basic data scrambler disclosed in the cited copending patent application; FIG. 2 is a generalized block diagram of the improved data scrambler according to this invention; FIG. 3 is a block diagram of a single-counter data scrambler according to this invention; FIG. 4 is a block diagram of